Hi all,
I'm trying to run a simulation but for some reason, something is wrong
there...
I have all my files compiled with no errors (finally).

Now, the simulation gets stuck at my Clock Divider portion. I
configured the input clock to be "clock" (rightclick menu of the
signal at the "Wave" window)
but for some reason, the other signals are not initializing correctly.

Can you tell what am I doing wrong or what have I missed?

Thanks,
Eyal.

the VHDL code is:

library ieee;
use ieee.std_logic_1164.all;

entity ClockDivider is
port(Clk       : in  std_logic;
     ClockDiv2 : out std_logic
     );
end ClockDivider;

architecture ClockDivider_arch of ClockDivider is
signal tempclk : std_logic;
begin
tempclk <= '0';
main : process(Clk)
begin

if (Clk'event and Clk='1') then
   tempclk<=not tempclk;
end if;
ClockDiv2<=tempclk;
end process main;
end ClockDivider_arch;

Hi Eyal,

The way your model is structure produces a conflict on the tempclk  
signal.  The assignment

     tempclk <= '0';

is providing a constant '0' driver while the main: process is driving  
a different value.  The main: process's driving value is initially  
'U', so the combined resolved value of tempclk will be 'X'.

The simplest solution is to eliminate the tempclk <= '0' assignment  
and instead, initialize the tempclk signal in it's declaration:

     signal tempclk : std_logic := '0';

This will reduce the number of drivers from 2 to 1.

-Brian

On Jun 30, 2008, at 7:02 AM, eoz...@gmail.com wrote: